Embedded dense memory is desired in many applications, including microprocessors. Semiconductor memories used within microprocessors are generally comprised of a memory cell array. A memory cell array may include a plurality of memory cells arranged in rows and columns, with each memory cell coupled to a corresponding wordline and a corresponding bitline of the semiconductor memory. Multiple transistor static random access memory (SRAM) is one example of a semiconductor memory that includes a memory cell array. Unfortunately, multiple transistor SRAMs, such as a six transistor (6T) SRAM, provide insufficient density to be used within embedded dense memories.
Semiconductor memory using one transistor (1T) body storage cells as memory cells provide better density than multiple transistor SRAMs. A 1T body storage memory cell generally stores data within a transistor body. The 1T memory cell generally uses different body voltages to store logic “0” and logic “1” values. Typically, writing both a logical 0 and a logical 1 to an array of 1T memory cells is performed separately in two phases. In other words, a first phase is provided to write, for example, the logic 0 values and a second phase is provided to write logic 1 values within the 1T body storage cells of the memory cell array.
Unfortunately, accessing of the transistor body to store data can be difficult because the body of the 1T memory cells may be tied to a supply voltage (Vcc) for a p-type metal oxide semiconductor (PMOS) device or tied to ground for an n-type metal oxide semiconductor (NMOS) device. When the body is not tied to either Vcc or ground, the body may float. As a result, the two-phase write cycle for writing a logic 1 value and a logic 1 value to a body storage cell array is performed by conventional memories.
Writing a new value to an IT memory cell requires altering of the transistor body voltage. One technique for altering the body voltage is using impact ionization current in one phase and a forward biased diode in another phase to perform a write operation to the 1T body storage memory cell. The use of a forward biased diode can cause a disturbance to other unselected memory cells during a write operation.